Calculate a Gen1–5 one-direction line payload bound and compare requested lanes with an entered platform budget.
Compute & memory
PCIe negotiated link and lane ledger
Calculate a Gen1–5 one-direction line payload bound and compare requested lanes with an entered platform budget.
Example inputs · Replace these with your measurements to build your plan.
Method, example and sources
Choose the lower documented host/card generation and narrower electrical width.
Apply Gen1/2 8b/10b or Gen3–5 128b/130b coding to the transfer rate, then convert bits to bytes in one direction.
Count links and other reserved lanes against the explicitly identified platform pool.
Verify slot wiring, bifurcation, sharing and firmware against the exact board before promising a configuration.
Worked example. A Gen4 x4 link has a one-direction line payload bound of about 7.877 GB/s before packet overhead. Two such links request eight lanes; reserving four other lanes uses twelve of an entered sixteen-lane pool.
The slower generation and narrower electrical width bound each link; platform routing still decides the actual negotiated layout.
Negotiated generation bound
4
Electrical width bound
4lanes
One-direction payload bound per link
7.877GB/s
Requested/reserved lanes
12
Unallocated lane budget
4
PCIe negotiated link and lane ledger: detailed result
Check
Result
Requested lanes within pool
Within entered limits
Board sharing / adapter support
Unknown
Application throughput
Not predicted by line rate
GB/s is decimal and one direction. Packet overhead, storage/controller limits and shared chipset uplinks reduce application throughput.
A passive adapter cannot create unsupported bifurcation. This model deliberately stops at Gen5; Gen6 uses different coding and transaction behavior.
From the catalog
Network Interface Cards
Explore related listings, then confirm the exact model requirements against your plan. These listings are not an automatic compatibility or capacity verdict.
Use the catalog search inside the worksheet to choose a model or compare the full product family.
The length of a PCIe connector does not establish its electrical lane count. A card and host negotiate within both devices’ generation and width limits, so an x16-shaped slot can still provide fewer lanes. This worksheet keeps the line-rate calculation separate from the platform lane ledger, avoiding a promise that every physically installed card runs at its maximum.
Before choosing a product
Motherboards can share lanes between slots, M.2 sockets and chipset links, and some adapters depend on exact bifurcation support. Check the board revision, installed processor, firmware and population table before accepting the ledger. The calculated payload is one-direction theoretical link capacity, not measured SSD or GPU application performance. Different transaction sizes, controller behavior and shared upstream paths can become the real bottleneck.
Worked example
A Gen4 x4 link has a one-direction line payload bound of about 7.877 GB/s before packet overhead. Two such links request eight lanes; reserving four other lanes uses twelve of an entered sixteen-lane pool.
